Notice Board: Call for Paper Vol. 8 Issue 10      Submission Start Date: September 30, 2021      Acceptence Notification Start: October 12, 2021      Submission End: October 18, 2021      Final MenuScript Due: October 22, 2021      Publication Date: October 31, 2021






Volume 5 Issue 7

Author Name
Anoop Kumar khambra, B.B. Soni
Year Of Publication
2018
Volume and Issue
Volume 5 Issue 7
Abstract
The increasing demand for low power mobile computing and consumer electronics products has refocused VLSI design in the last two decades on lowering power and increasing energy efficiency. Power reduction is treated at all design levels of VLSI chips. From the architecture through block and logic levels, down to gate level circuit and physical implementation, one of the major dynamic power consumers in the system clock signal, typically responsible for up to 50% of the total dynamic power consumption. Clock network design is a delicate procedure and is therefore done in a very conservative manner under worst case assumptions. It incorporates many diverse aspects such as selection of sequential elements, controlling the clock skew, the decision of the topology and physical implementation of the clock distribution network.
PaperID
2018/05/IJMERT/7/338

Author Name
Anoop Kumar khambra, B.B. Soni, Puran Gour
Year Of Publication
2018
Volume and Issue
Volume 5 Issue 7
Abstract
Data driven gating is causing area and power overheads that must be considered. To reduce the overhead, it is proposed to group several FFs to be driven by the same clock signal, generated by bring the enabling signals of the individual FFs. This may however, lower the disabling effectiveness. In a recent paper, a model for data-driven gating is developed based on the toggling activity of the constituent FFs. The optimal fan-out of a clock gate yielding maximal power savings is derived based on the average toggling statistics of the individual FFs, process technology, and cell library in use. Data driven clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. When a logic unit is clock, its underlying sequential elements receive the clock signal regardless of whether they will toggle in the next cycle. In this flip-flop are grouped so that they share a common clock enabling signal to reduce the hardware overhead and power consumptio
PaperID
2018/05/IJMERT/7/339

Author Name
Nupur Agrawal, Surendra Vishwakarma
Year Of Publication
2018
Volume and Issue
Volume 5 Issue 7
Abstract
In current decade, digital images are in use in a wide range of applications and for multiple purposes. They also play an important role in the storage and transfer of visual information, especially the secret ones. With this widespread usage of digital images, in addition to the increasing number of tools and software of digital images editing, it has become easy to manipulate and change the actual information of the image. Therefore, it has become necessary to check the authenticity and the integrity of the image by using modern and digital techniques, which contribute to analysis and understanding of the images’ content, and then make sure of their integrity. There are many types of image forgery, the most important and popular type is called copy-move forgery, which uses the same image in the process of forgery.
PaperID
2018/05/IJMERT/7/341

Author Name
Anushri Bangilwar, Mukesh Saini
Year Of Publication
2018
Volume and Issue
Volume 5 Issue 7
Abstract
The acceptability and diversity of sensors in every filed of engineering. The success story of sensors depends on life of sensor network. The sensor network provides service of iots application on user side. In sensor network the utilization of energy is measure issue. The maximum utilization of energy enhanced the life of iots application. in this paper present the review of wireless sensor network in different domain mode of energy harvesting. The process of energy harvesting LEACH protocol is basic protocol for the sensor network
PaperID
2018/05/IJMERT/7/342



Notice Board :

Call for Paper
Vol. 8 Issue 10

Submission Start Date:
September 30, 2021

Acceptence Notification Start:
October 12, 2021

Submission End:
October 18, 2021

Final MenuScript Due:
October 22, 2021

Publication Date:
October 31, 2021