DESIGN AND IMPLEMENTATION OF AREA EFFICIENT LATTICE BASED CRYPTOGRAPHY

Abstract

With a recent increase in the advancement of the technology, computer system and it’s sensitive data are getting exhibited to unauthorized users, with steadily corroding the fundamentals of computer security. This, in fact, demanded fundamental innovations that require several cryptographic paradigms and security protocol. The interest in lattice-based cryptography is increasing due to its quantum resistance and its provable security under some worst-case hardness assumptions. As this is a relatively new topic, the search for efficient hardware architectures for lattice based cryptographic building blocks is still an active area of research. Therefore implementation of hardware efficient lattice based cryptography is proposed in this project. This lattice based cryptography architecture is implemented by using the Number Transform Theory (NTT) for area optimizations to the most critical and insensitive operation applications. The proposed hardware architectures can reduce slice usage, number of utilized memory blocks and total memory accesses by using a simplified address generation, improved memory organization. Compared to prior work, with similar performance the proposed hardware architectures can save number of occupied slices, used memory blocks and can fit into smallest Xilinx Spartan-6 FPGA.