EFFICIENT HIGH-RESOLUTION SEGMENTED SIGMA DELTA-DAC FOR BUILT-IN SELF-TEST INTEGRATION

Abstract

Sigma-delta (ΣΔ) digital-to-analog converters (DACs) are widely favored for
implementing programmable DC voltage generators within built-in self-test (BIST)
setups due to their superior linearity. However, traditional ΣΔ-DACs typically demand
considerable digital memory and entail the use of reconstruction filters with a
substantial silicon footprint. To address these limitations, this study proposes a novel
segmented DAC architecture that employs two sub-DACs, both utilizing ΣΔ
technology. This innovative architecture offers a twofold advantage: reduction in filter
footprint size and significant savings in memory usage, thereby streamlining BIST
implementation. The efficacy of the segmented ΣΔ-DAC architecture is demonstrated
through the development of two experimental prototypes. The first prototype is an
integrated circuit (IC) design fabricated using TSMC 65-nm CMOS technology.
Results indicate that the IC achieves a resolution of 12 bits utilizing only 1020 memory
elements, in contrast to an unsegmented ΣΔ-DAC, which requires 4095 elements for
comparable resolution—a noteworthy 75% reduction in memory utilization. Moreover,
the segmented prototype occupies a silicon area of 0.5 mm^2, whereas the unsegmented
design requires 0.77 mm^2 for the same resolution, representing a significant 35%
reduction in silicon area. A second prototype implements the segmented ΣΔ-DAC
architecture using discrete components. This discrete prototype achieves a resolution
of 16 bits with just 1020 memory elements, whereas the unsegmented counterpart
necessitates 65,535 bits for equivalent resolution—a remarkable 98% reduction in
memory usage. These findings underscore the promising prospects of the proposed segmented ΣΔ-DAC architecture, making it a compelling candidate for publication in
leading academic journals.